1. Field of the Invention
The invention relates to a semiconductor device comprising a single-ended sense amplifier circuit amplifying data that is stored in a current change memory cell and is read out to a bit line.
2. Description of Related Art
A current change memory cell has been conventionally known, which stores data in accordance with an amount of current flowing through a selected memory cell. In a semiconductor device using this type of memory cell, it is desirable to employ a single-ended sense amplifier having a small circuit scale instead of a differential type sense amplifier in terms of shrinking chip area. Further, miniaturization of the memory cell requires a low voltage operation, in which it is desirable to supply a potential as low as possible to the bit line connected to the memory cell.
For example, Patent Reference 1 discloses a semiconductor device having memory cells each storing data in accordance with a resistance value between a signal input/output terminal and a power supply terminal and having a single-ended sense amplifier that amplifies a signal outputted from the input/output terminal using one MOS transistor (Q1). By using the sense amplifier shown in Patent Reference 1, it is possible to reduce a capacitance value of bit lines in a read operation of the memory cells.
Further, for example, Patent Reference 2 discloses a configuration in which a MOS transistor functioning as a charge transfer gate is disposed between a bit line connected to memory cells and a sense node at an input of a single-ended sense amplifier. By employing the sense amplifier configured in this manner, it is possible to secure operating margin required for the amplifying operation of the sense amplifier in a read operation of the memory cells.    [Patent Reference 1] Japanese Patent Application Laid-open No. 2009-259379 (U.S. Pub. No. 2009/0257268 A1)    [Patent Reference 2] Japanese Patent Application Laid-open No. 2010-55730 (U.S. Pub. No. 2010/0061170 A1)
However, according to the technique disclosed in Patent Reference 1, when the sense amplifier drives an output node connected to a global bit line, a gate voltage of the MOS transistor (Q1) is limited lower than a precharge voltage of the bit line or lower than a voltage supplied to the memory cells. Therefore, when the gate voltage is decreased with miniaturization of the memory cells, there causes a decrease in speed with which the sense amplifier drives the global bit line. Meanwhile, according to the technique disclosed in Patent Reference 2, when the charge is transferred between the bit line and the sense node via the charge transfer gate (Q1), potential settings for the bit line and the sense node cannot be independently performed, which causes that reading speed is decreased when the potential of the bit line is lowered with the miniaturization of the memory cells. In this manner, the conventional configuration cannot achieve a semiconductor device capable of a high-speed read operation with lowering the potential for the bit lines in the read operation of the current change memory cell.